View LH530800A_497257.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LH530800A
FEATURES * 131,072 words x 8 bit organization * Access time: 150 ns (MAX.) * Power consumption: Operating: 192.5 mW (MAX.) Standby: 550 W (MAX.) * Static operation * TTL compatible I/O * Three-state outputs * Single +5 V power supply * Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 450-mil QFJ (PLCC) * JEDEC standard EPROM pinout (DIP) DESCRIPTION
The LH530800A is a mask-programmable ROM organized as 131,072 x 8 bits (1,048,576 bits). It is fabricated using silicon-gate CMOS process technology.
32-PIN DIP 32-PIN SOP
CMOS 1M (128K x 8) MROM
PIN CONNECTIONS
TOP VIEW
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Vcc NC NC A14 A13 A8 A9 A11 OE/OE A10 CE D7 D6 D5 D4 D3
530800A-1
Figure 1. Pin Connections for DIP and SOP Packages
32-PIN QFJ TOP VIEW
VCC
A12
A15
A16
NC
NC
4 A7 A6 A5 A4 A3 A2 A1 A0 D0 5 6 7 8 9 10 11 12 13
3
2
1
32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE/OE A10 CE D7
14 15 16 17 18 19 20
D1
GND
D2
D3
D4
D5
D6
NC
530800A-7
Figure 2. Pin Connections for QFJ (PLCC) Package
1
LH530800A
CMOS 1M Mask-Programmable ROM
A16 2 A15 3 A14 29
A10 23 A9 26 A8 27 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12
ADDRESS DECODER
ADDRESS BUFFER
A13 28 A12 4 A11 25
MEMORY MATRIX (131,072 x 8)
COLUMN SELECTOR
SENSE AMPLIFIER
CE 22
CE BUFFER
TIMING GENERATOR OUTPUT BUFFER
OE/OE 24
OE BUFFER 32 16 VCC GND 13 D0 14 D1 15 D2 17 D3 18 D4 19 D5 20 D6 21 D7
530800A-2
Figure 3. LH530800A Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME NOTE SIGNAL PIN NAME NOTE
A0 - A16 D0 - D7 CE OE/OE
Address input Data Output Chip enable input Output enable input 1 1
VCC GND NC
Power supply (+5 V) Ground No connection
NOTE: 1. Active level of OE/OE is mask-programmable.
TRUTH TABLE
CE OE/OE MODE D0 - D7 SUPPLY CURRENT NOTE
H L L
NOTE: 1. X = H or L.
X L/H H/L
Non selected Non selected Selected
High-Z High-Z DOUT
Standby (ISB) Operating (ICC) Operating (ICC)
1
2
CMOS 1M Mask-Programmable ROM
LH530800A
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Supply voltage Input voltage Output voltage Operating temperature Storage temperature
VCC VIN VOUT Topr Tstg
-0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 0 to +70 -65 to +150
V V V C C
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage
VCC
4.5
5.0
5.5
V
DC CHARACTERISTICS (VCC = 5 V 10%, TA = 0 to +70C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input `Low' voltage Input `High' voltage Output `Low' voltage Output `High' voltage Input leakage current Output leakage current
VIL V IH VOL VOH | ILI | | ILO | ICC1 ICC2 ICC3 ICC4 ISB1 ISB2 CIN COUT I OL = 2.0 mA I OH = -400 A V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 150 ns t RC = 1 s t RC = 150 ns t RC = 1 s CE = VIH CE = VCC - 0.2 V f = 1 MHz T A = 25C
-0.3 2.2 2.4
0.8 VCC + 0.3 0.4 10 10 35 25 30 20 2 100 10 10
V V V V A A mA mA mA A pF pF 1 2 3
Operating current
Standby current Input capacitance Output capacitance
NOTES: 1. CE/OE = VIH or OE = VIL 2. VIN = VIH or VIL, CE = VIL, outputs open 3. VIN = (VCC - 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
AC CHARACTERISTICS (VCC = 5 V 10%, TA = 0 to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Read cycle time Address access time Chip enable time Output enable time Output hold time CE to output in High-Z OE to output in High-Z
tRC tAA tACE tOE tOH tCHZ tOHZ
150 150 150 70 5 70 70
ns ns ns ns ns ns ns 1
NOTE: 1. This is the time required for the output to become high-impedance.
3
LH530800A
CMOS 1M Mask-Programmable ROM
AC TEST CONDITIONS
PARAMETER RATING
Input voltage amplitude Input rise/fall time Input reference level Output reference level Output load condition
0.6 V to 2.4 V 10 ns 1.5 V 0.8 V and 2.2 V 1TTL +100 pF
tRC
A0 - A16 tAA (NOTE)
CE tACE (NOTE) OE OE tOE (NOTE) tOHZ tCHZ
D0 - D7
DATA VALID
tOH NOTE: Data becomes valid after tAA, tACE, and tOE from address input, chip enable and output enable, respectively have been met.
530800A-3
Figure 4. Timing Diagram
4
CMOS 1M Mask-Programmable ROM
LH530800A
PACKAGE DIAGRAMS
32DIP (DIP032-P-0600)
32 17
DETAIL
13.45 [0.530] 12.95 [0.510]
1 41.30 [1.626] 40.70 [1.602]
16 0.30 [0.012] 0.20 [0.008]
0 TO 15
4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT
15.24 [0.600] TYP.
DIMENSIONS IN MM [INCHES]
32DIP
32-pin, 600-mil DIP
32SOP (SOP032-P-0525)
1.27 [0.050] TYP. 1.40 [0.055] 17
0.50 [0.020] 0.30 [0.012]
32
11.50 [0.453] 11.10 [0.437]
14.50 [0.571] 13.70 [0.539]
12.50 [0.492]
1 20.80 [0.819] 20.40 [0.803]
16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
32SOP
32-pin, 525-mil SOP
5
LH530800A
CMOS 1M Mask-Programmable ROM
32QFJ (QFJ032-P-R450)
29 21
30
20
1
11.40 [0.449]
12.50 [0.492] 12.30 [0.484]
10.90 [0.429] 10.10 [0.398]
4
14
5 14.00 [0.551] 15.10 [0.594] 14.90 [0.587]
13
0.25 [0.010] 1.20 [0.047] 1.20 [0.047] 3.50 [0.138] 2.30 [0.091] 3.10 [0.122] 1.90 [0.075]
1.27 [0.050] TYP.
0.56 [0.022] 0.36 [0.014] 13.50 [0.531] 12.70 [0.500]
DIMENSIONS IN MM (INCHES)
MAXIMUM LIMIT MINIMUM LIMIT
32QFJ450
32-pin, 450-mil QFJ (PLCC)
ORDERING INFORMATION
LH530800A Device Type X Package D 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) U 32-pin, 450-mil QFJ (PLCC) (QFJ032-P-R450)
CMOS 1M (128K x 8) Mask Programmable ROM Example: LH530800AD (CMOS 1M (128K x 8) Mask Programmable ROM, 32-pin, 600-mil DIP)
530800A-6
6

▲Up To Search▲

Price & Availability of LH530800A

	To Download LH530800A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .